About us

SemiconTantra Conference – 2026 is Technical Conference in the Semiconductor Domain intended to bring in Academia and Research community, Industry Professionals and Startups on one platform to discuss, deliberate and showcase advancements and trends in Semiconductor Design for AI Enabled Systems. Students, Industry Professionals, Startups from both Chip Design and System Design companies are expected to benefit from this conference and apply these learnings to design and Develop next generation products for AI enabled Systems.

Important Dates

Wed, Jun 10, 2026

Abstract registration deadline

Wed, Jun 10, 2026

Submission deadline

Tue, Jun 30, 2026

Notification of Acceptance

Fri, Jul 31, 2026

Camera-ready Paper Submission

Sat, Aug 22, 2026

Conference Date

Paper Submission

Research Paper Submission Tracks

Ai enabled computing

Advanced circuit design

Chip design for ai hardware

Hardware platform for ai acceleration

Analog, digital, and mixed-signal circuits for AI workloads

High-speed, low-power, and energy-efficient circuit techniques

Memory circuits (SRAM, DDR/HBM, NVM) for AI accelerators

Clocking, power management, and signal integrity

Reliability, variability, and testability at advanced nodes

Advanced CMOS and post-CMOS devices

Emerging devices (FinFET, GAAFET, TFET, CNTFET, memristors)

Device modelling and characterization for AI applications

3D integration, heterogeneous integration, and packaging

Co-Packaged Optics

Processor, accelerator, memory, and interface IPs

IP verification, validation, and security

Reusable and configurable IP frameworks

Licensing, standardization, and interoperability challenges

SoC architectures for edge, cloud, and embedded AI

Heterogeneous computing (CPU–GPU–NPU integration)

High Performance SoC Fabric and Memory Subsystems

HW–SW co-design and system-level optimization

Performance, power, and area (PPA) trade-offs

AI hardware platforms and development boards

FPGA- and ASIC-based AI platforms

Platform-level optimization and benchmarking

Deployment frameworks for edge and embedded AI

Case studies and real-world system implementations

EDA tools for circuit, IP, and SoC design

Efficiency and Productivity Boost with AI-assisted Chip Design

Hardware Security, trusted IP, and secure SoCs

Safety-critical AI systems (automotive, medical, industrial)

Call for Papers Description

All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome: Full papers, Posters. Theme: Semiconductor Design and Hardware Platforms for AI-Enabled Intelligent Systems