About us

The Workshop on Post-Quantum Cryptography and Secure Hardware (WPQC) is a dedicated forum for researchers and practitioners in hardware security, EDA/CAD, computer architecture, and cryptography, exploring the intersection of PQC and hardware/system design.

Important Dates

Fri, Oct 10, 2025

Submission Deadline (Extended)

Wed, Oct 15, 2025

Acceptance Notification

Mon, Oct 20, 2025

Camera-ready Deadline

Thu, Oct 30, 2025

Workshop Date

Paper Submission

Research Paper Submission Tracks

Hardware/software co-design for PQC resilience

Secure accelerator design and countermeasure techniques

Microarchitectural security for PQC workloads

Side-Channel Attacks (SCA) on PQC: Power, EM, timing, cache, etc.

Fault Injection Attacks (e.g., laser, clock glitch, DVFS) on PQC

Resilience Mechanisms: Countermeasures against SCA/faults

Hardware Trojans in PQC Accelerators

Hardware Trojans and backdoor analysis in PQC IP

Secure PQC Accelerator Design & Deployment

Design automation for PQC SoCs and accelerators

Low-power and area-optimized implementations of PQC

Hardware/software co-design for PQC primitives

EDA tools and flows for PQC integration

PQC-aware hardware synthesis & optimization

Power/thermal analysis for PQC implementations

Formal verification of PQC implementations

Verifiable computation with PQC

Equivalence checking and hardware compliance with NIST PQC standards

PQC in embedded systems, IoT, and automotive domains

Quantum-safe firmware, secure boot, and key management

PQC deployment in cloud and edge computing

System-on-Chip (SoC) integration of PQC primitives

Post-Quantum secure architectures for AI/ML workloads

Benchmarking frameworks for PQC evaluation

Open-source EDA flows and simulation tools for PQC

Fault models and evaluation metrics for post-quantum circuits

Quantum-aware hardware design and CAD tools

Machine learning for side-channel analysis on PQC

Side-channel analysis of quantum neural networks

Quantum-safe security for supply chains

PQC in AI/neuromorphic and emerging computing architectures

Call for Papers Description

The following categories are welcome to submit as a two-page extended abstract: Industry and academic expert talks and demos, Panel discussion, Student presentations and posters. Submissions of workshop/conference papers with/without archived proceedings, previously published journal papers, or pre-prints are allowed.